Re: [OpenSPARC general] Re: Geting the core1 verilog code. - Shrenik Mehta (Frontend Technologies & OpenSPARC) |
regression suite problem - Giacomo BERNARDI |
Platform Basics, a very, very basic question. - gene...@opensparc.info |
description - gene...@opensparc.info |
Re: description - gene...@opensparc.info |
Re: Platform Basics, a very, very basic question. - gene...@opensparc.info |
Re: Platform Basics, a very, very basic question. - gene...@opensparc.info |
Re: Platform Basics, a very, very basic question. - gene...@opensparc.info |
Re: Platform Basics, a very, very basic question. - gene...@opensparc.info |
About the Roll back mechanism - gene...@opensparc.info |
Re: help with simulating benchmark programs in openSparc T1 - gene...@opensparc.info |
Architectural Transplant Project Release - gene...@opensparc.info |
What does the top level instance name "iop" mean? - gene...@opensparc.info |
boot device:net file and args: Timeout Waiting for ARP/PARP packet - gene...@opensparc.info |
Re: boot device:net file and args: Timeout Waiting for ARP/PARP packet - gene...@opensparc.info |
How can i run just one moderate size regression test for thread1_mini ? - gene...@opensparc.info |
How to get a vcd or fsdb dump? - gene...@opensparc.info |
Are there any known issues when using cadence/sim/05.30-s006 NC-Sim ? - gene...@opensparc.info |
How to run a test in interactive mode? - gene...@opensparc.info |
Re: How can i run just one moderate size regression test for thread1_mini ? - gene...@opensparc.info |
Re: How can i run just one moderate size regression test for thread1_mini ? - gene...@opensparc.info |
Re: Are there any known issues when using cadence/sim/05.30-s006 NC-Sim ? - gene...@opensparc.info |
Re: [OpenSPARC general] Question about Sun's Processors - Rayson Ho |
Re: Question about Sun's Processors - gene...@opensparc.info |
Re: Question about Sun's Processors - gene...@opensparc.info |