On 13/01/2005 17:12, Mikael Abrahamsson wrote:
On Thu, 13 Jan 2005, Tim Stevenson wrote:
This card is not fully non-blocking, but it is nearly (like >98%) line
rate on all 4 ports with large packets. You can't ever get full 40G wire
ethernet across the fabric, as we add 32 bytes of overhead to every
packet. Also, the fwding engine is the bottleneck at 64B packets, ie,
either the sup (30Mpps) or a DFC3 (48Mpps) has less capacity than 4x10G
ports (60Mpps).
But in the case of i-mix (avg 300 byte packets) it's able to do at least
90% of all ports? Is there any combination of ports that are bundled
together asic-wise or channelwise on the 6704, or are all ports equal in
respect to each other?
From what I've read, the 6704 has two ports on each ASIC, and each ASIC
is capable of 10Gb/s each when *not* helped by a dCEF720 daughter card.
(So, you can do a total of 10Gb/s across ports 1 and 2 combined and
10Gb/s across 3 and 4 combined) I'm guessing the bottleneck is shoving
enough data to the Supervisor and back to switch a packet centrally,
which is why the daughtercard improves performance.
I might of couse be totally wrong, I'd like to see detailed block
diagrams on cisco.com for this sort of thing so we know how fast the
cards really are and also to aid in troubleshooting but I can't see it
happening.
I'm not losing my mind, no I'm not changing my lines,
I'm just learning new things with the passage of time
19 messages in net.nether.puck.cisco-nsp[c-nsp] Cisco 6509 and Bus speeds
