11 messages in org.freebsd.freebsd-smpRe: Good SMP Motherboards| From | Sent On | Attachments |
|---|---|---|
| Bruce Albrecht | Nov 3, 1999 7:31 am | |
| David Scheidt | Nov 3, 1999 9:48 am | |
| Oliver Fromme | Nov 3, 1999 4:05 pm | |
| Daniel O'Connor | Nov 3, 1999 4:19 pm | |
| David Scheidt | Nov 3, 1999 4:34 pm | |
| Keith Chiem | Nov 3, 1999 4:38 pm | |
| Joachim Strombergson | Nov 3, 1999 11:36 pm | |
| Bob Bishop | Nov 4, 1999 1:31 am | |
| Remy Nonnenmacher | Nov 4, 1999 4:04 am | |
| Thierry Herbelot | Nov 4, 1999 5:38 am | |
| Tom Embt | Nov 4, 1999 6:11 pm |
| Subject: | Re: Good SMP Motherboards | |
|---|---|---|
| From: | Thierry Herbelot (thie...@alcatel.fr) | |
| Date: | Nov 4, 1999 5:38:25 am | |
| List: | org.freebsd.freebsd-smp | |
Salut,
Remy Nonnenmacher wrote:
[COUIC]
- Linear interpolation for a Celeron 500 would lead to 2.80 Mkey/s which is nearly what gave the PIII. If this is exact, the performance/price ratio is outstanding.
This is exactly what I get with my BP6 and a pair of 333 O'Cd @ 500 MHz, happily crunching for about one month, under the then-Current (the rc5 run was at the beginning just a test to validate the cooling system of the box - I have to find time to try 550 MHz)
TfH
- This is a pure core test. Do not expect same ratio on dayly operations. - David Malone have a really interesting graph that shows impact of cache size and RAM speed over a core-intensive process. It can be found at : http://www.maths.tcd.ie/~dwmalone/comp/perf.ps and shows the L1, L2 and RAM speed and size steps.
Speculation:
Intel build the same core every time. If the cache runs full speed, it's a Xeon. If only half of the cache runs at full speed, it's a PIII, if a quarter of the cache runs at full speed it's a celeron. If the cache runs at half speed, it's a PII. If nothing works, back to the fundry.
Probably exagerated, but it's the basic idea.
RN. IeM
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