atom feed17 messages in org.freebsd.freebsd-archWhere do MSI quirks belong? [patch]
FromSent OnAttachments
John PolstraNov 20, 2006 4:11 am 
John BaldwinNov 20, 2006 6:45 pm 
John PolstraNov 20, 2006 6:49 pm 
John BaldwinNov 20, 2006 9:07 pm 
Jack VogelNov 20, 2006 11:44 pm 
John PolstraNov 20, 2006 11:59 pm 
Jack VogelNov 21, 2006 12:02 am 
John PolstraNov 21, 2006 12:06 am 
John PolstraDec 10, 2006 4:28 pm 
Andre OppermannDec 11, 2006 2:30 am 
John BaldwinDec 11, 2006 6:57 am 
John PolstraDec 11, 2006 3:24 pm 
John PolstraDec 11, 2006 3:32 pm 
John BaldwinDec 12, 2006 12:21 pm 
John PolstraDec 13, 2006 3:31 pm 
John PolstraDec 13, 2006 5:56 pm 
John BaldwinDec 14, 2006 9:41 am 
Subject:Where do MSI quirks belong? [patch]
From:John Baldwin (jh@freebsd.org)
Date:Dec 11, 2006 6:57:11 am
List:org.freebsd.freebsd-arch

On Sunday 10 December 2006 19:29, John Polstra wrote:

On Nov 20, 2006, at 9:42 AM, John Baldwin wrote:

It's going to be a function of the chipset, as something in the chipset (presumably a Host -> PCI bridge) has to listen for writes to 0xfeeXXXXXX and convert them into APIC messages. There are two ways I planned on doing this:

1) Allow PCI-PCI bridges to be blacklisted, and the pcib_alloc_msi [x]() methods would compare the bridge's device id against a blacklist. This can matter if you have virtual PCI-PCI bridges that really a HT -> PCI bridge or the like.

2) Blacklist chipsets in the x86 MD code based on the device ID of the first Host -> PCI bridge at device 0.0.0.

I have implemented both of these checks, except that I put #2 into the MI code since I couldn't find any reason to make it x86- specific. Here's the patch. Does it look OK to you? It works fine here.

Hmm. I did blacklist stuff several weeks ago but haven't had time to test it or post it yet. :( I do think I like your approach a bit better though. What I had so far is here:

http://www.FreeBSD.org/~jhb/patches/msi_blacklist.patch

I'm not sure if it's worth blacklisting MSI separate from MSI-X as that only makes a difference at the device level (chipsets just get a single memory write per interrupt either way, they can't tell MSI from MSI-X).