-----Original Message----- From: Tian, Kevin [mailto:kevi...@intel.com] Sent: Monday, September 19, 2005 8:18 AM To: Tian, Kevin; Magenheimer, Dan (HP Labs Fort Collins) Cc: xen-...@lists.xensource.com Subject: RE: [Xen-ia64-devel] RE: Latest status about multiple domains on XEN/IPF

Now I found the issue coming from the event injection mechanism. Actually under some circumstance, the evtchn_upcall_pending and some evtchn_pending will be set on but related irr bit is cleared. Once this condition happens, later event notification always failed to enable irr bit. The reason comes from guest who may re-generate event ignored before and this path has nothing to do with irr however. Based upon following rough patch, I can see event injected into guest however, to see nested event injection and dead lock happening. So may need a bit more investigation. If this mechanism can be promised to work again, we may see something interesting happen since previous progress was completely triggered by "xm console" instead of event.

[Xen] diff -r 55bc6698c889 xen/arch/ia64/xen/domain.c --- a/xen/arch/ia64/xen/domain.c Thu Sep 15 00:00:23 2005 +++ b/xen/arch/ia64/xen/domain.c Mon Sep 19 22:02:27 2005 @@ -916,7 +916,7 @@ #endif

/* Mask all upcalls... */ - for ( i = 0; i < MAX_VIRT_CPUS; i++ ) + for ( i = 1; i < MAX_VIRT_CPUS; i++ ) d->shared_info->vcpu_data[i].evtchn_upcall_mask = 1;

#ifdef CONFIG_VTI diff -r 55bc6698c889 xen/arch/ia64/xen/vcpu.c --- a/xen/arch/ia64/xen/vcpu.c Thu Sep 15 00:00:23 2005 +++ b/xen/arch/ia64/xen/vcpu.c Mon Sep 19 22:02:27 2005 @@ -21,6 +21,7 @@ #include <asm/processor.h> #include <asm/delay.h> #include <asm/vmx_vcpu.h> +#include <xen/event.h>

typedef union { struct ia64_psr ia64_psr; @@ -631,6 +632,16 @@ { UINT64 *p, *q, *r, bits, bitnum, mask, i, vector;

+ /* Always check pending event, since guest may just ack the + * event injection without handle. Later guest may throw out + * the event itself. + */ + if (event_pending(vcpu) && + !test_bit(vcpu->vcpu_info->arch.evtchn_vector, + &PSCBX(vcpu, insvc[0]))) + test_and_set_bit(vcpu->vcpu_info->arch.evtchn_vector, + &PSCBX(vcpu, irr[0])); + p = &PSCBX(vcpu,irr[3]); /* q = &PSCB(vcpu,delivery_mask[3]); */ r = &PSCBX(vcpu,insvc[3]);

[XENO] diff -r c9522a6d03a8 drivers/xen/core/evtchn_ia64.c --- a/drivers/xen/core/evtchn_ia64.c Wed Sep 14 23:35:51 2005 +++ b/drivers/xen/core/evtchn_ia64.c Mon Sep 19 22:04:04 2005 @@ -81,6 +81,7 @@ shared_info_t *s = HYPERVISOR_shared_info; vcpu_info_t *vcpu_info = &s->vcpu_data[smp_processor_id()];

+ vcpu_info->evtchn_upcall_mask = 1; vcpu_info->evtchn_upcall_pending = 0;

/* NB. No need for a barrier here -- XCHG is a barrier on x86. */ @@ -107,6 +108,7 @@ } } } + vcpu_info->evtchn_upcall_mask = 0; return IRQ_HANDLED; }

Thanks, Kevin