8 messages in com.xensource.lists.xen-ia64-develRE: [Xen-ia64-devel] [PATCH] Remove F...
FromSent OnAttachments
Masaki Kanno24 Apr 2006 04:38.patch
Xu, Anthony25 Apr 2006 00:02 
Masaki Kanno25 Apr 2006 08:26 
Tristan Gingold25 Apr 2006 08:33 
Xu, Anthony25 Apr 2006 20:49 
Masaki Kanno25 Apr 2006 22:31 
Alex Williamson25 Apr 2006 22:58 
Alex Williamson25 Apr 2006 23:36 
Subject:RE: [Xen-ia64-devel] [PATCH] Remove FORCE_CRASH from alt_itlb_miss
From:Xu, Anthony (anth@intel.com)
Date:04/25/2006 08:49:00 PM
List:com.xensource.lists.xen-ia64-devel

From: Masaki Kanno

Sent: 2006?4?25? 23:27 To: xen-@lists.xensource.com Subject: Re: [Xen-ia64-devel] [PATCH] Remove FORCE_CRASH from alt_itlb_miss

Hi Anthony,

Please teach me in detail.

For supporting discontinuous memory, ps in region register is always 16K, There are two implicit parameters for itc instruction, The other is cr.ifa indicating fault virtual address. One is cr.itir, cr.itir.ps determine the TLB page size, When dtlb_miss happens, cr.itir.ps = rr.ps (now this is 16K) But in identity mapping, we can use bigger page size to reduce tlb miss faults, Following is pseudo code for this cr.itir.ps = IA64_GRANULE_SHIFT itc.d // insert the TLB entry

I applied this patch and FPSWA supporting patch to Xen and tested it. Because I ran LTP on dom0, and a test about a floating point succeeded, I sent this patch. Your patch is correct. :-)

Best regards, Kan

Xu, Anthony wrote:

One comment, Since the page size of region 7 is 16K now, This patch make identity mapping based on 16K. Can we align with linux kernel using 16M identity mapping?

Thanks, -Anthony

-----Original Message----- From: xen-@lists.xensource.com [mailto:xen-@lists.xensource.com] On Behalf Of Masaki Kanno Sent: 2006?4?24? 19:39 To: xen-@lists.xensource.com Subject: [Xen-ia64-devel] [PATCH] Remove FORCE_CRASH from alt_itlb_miss

Hi,

This patch removed FORCE_CRASH from alt_itlb_miss handler.

Signed-off-by: Masaki Kanno <kann@jp.fujitsu.com>

Best regards, Kan