Saurabh Misra wrote:
Hi Saurabh,
What I concerned is, although CPU0 BSPL is 6 as you said. But CPU1 is
IDLE at time,
why those pending softcall can't be dispatched to CPU1?
The problem is that siron uses global inum to generate level1 on a
particular CPU. If level1 is already pending on CPU 0, CPU 1 wouldn't
fire level1 using siron() because IV_PENDING flag would be set in
interrupt vector table.
http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/sun4/ml/interrupt.s#1555
The other problem is that CPU 0 should poke CPU 1 to do softcall
processing in this case which does not happen in the current
implementation.
I think we are seeing some problem with e100g interrupt service
routine as well. It's taking longer time than usual which creates this
situation more often.
Thanks for your explanations.
But I do want to ensure the issue I ran into is exact same with the
issue you mentioned above. What should I check by using mdb next?
Finally, I've got two CPU's st_pending value in crash dump.
How can I ensure CPU0 will fire the softlevel1 interrupt from these value?
CPU0:
fffffffffbc27d10::print struct machcpu mcpu_softinfo
{
mcpu_softinfo.st_pending = 0x416
}
CPU 1:
fffffffffbc2f840::print struct machcpu mcpu_softinfo
{
mcpu_softinfo.st_pending = 0x404
}
Since CPU0's value is 0x416, it will generate the soft interrupts with
PIL 1, 2, 4, 10, whereas CPU1 will generate softint with 4 10, is it right?
I'm not sure whether my understand is right, please correct me if I'm wrong.
4 messages in org.opensolaris.mdb-discuss[mdb-discuss] [Fwd: [osol-code] Quest...
