19 messages in net.nether.puck.cisco-nsp[c-nsp] Cisco 6509 and Bus speeds
FromSent OnAttachments
Marcel LemmenJan 13, 2005 7:44 am 
Colin WhittakerJan 13, 2005 8:23 am 
Arnold NipperJan 13, 2005 8:32 am 
Paul SchopisJan 13, 2005 11:16 am 
Clinton WorkJan 13, 2005 11:17 am 
Arnold NipperJan 13, 2005 11:28 am 
Ethern M.C. LinJan 13, 2005 11:36 am 
Arnold NipperJan 13, 2005 11:42 am 
Tim WindersJan 13, 2005 11:43 am 
Tim StevensonJan 13, 2005 11:51 am 
Tim StevensonJan 13, 2005 11:51 am 
Tim StevensonJan 13, 2005 11:51 am 
Mikael AbrahamssonJan 13, 2005 12:12 pm 
Ryan O'ConnellJan 13, 2005 12:23 pm 
Ian CoxJan 13, 2005 3:38 pm 
Brad BoninJan 13, 2005 3:44 pm 
Tim StevensonJan 13, 2005 4:12 pm 
Paul SchopisJan 13, 2005 4:17 pm 
Michael LoftisJan 13, 2005 5:12 pm 
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Subject:[c-nsp] Cisco 6509 and Bus speedsActions...
From:Ian Cox (ic@cisco.com)
Date:Jan 13, 2005 3:38:35 pm
List:net.nether.puck.cisco-nsp

WS-X6704 has 2 x 20Gbps full duplex fabric channels, Ports 1 and 2 use fabric channel 0, and ports 3 and 4 use fabric channel 1. The addition of DFC3x on the card means packet lookups are performed by the DFCx increasing overall system performance.

Review the following test reports, which shows the performance possible with DFC3x and WS-X6724, WS-X6748, and WS-X6704 modules.

http://www.eantc.com/press/pressreleases/sep03/EANTC-Summary-Report-Cisco-10GE-Catalyst6500-Supervisor720.pdf http://www.eantc.com/press/pressreleases/sep03/EANTC-Summary-Report-Cisco-GigE-Catalyst6500-Supervisor720.pdf

Ian

At 05:23 PM 1/13/2005 +0000, Ryan O'Connell wrote:

On 13/01/2005 17:12, Mikael Abrahamsson wrote:

On Thu, 13 Jan 2005, Tim Stevenson wrote:

This card is not fully non-blocking, but it is nearly (like >98%) line rate on all 4 ports with large packets. You can't ever get full 40G wire ethernet across the fabric, as we add 32 bytes of overhead to every packet. Also, the fwding engine is the bottleneck at 64B packets, ie, either the sup (30Mpps) or a DFC3 (48Mpps) has less capacity than 4x10G ports (60Mpps).

But in the case of i-mix (avg 300 byte packets) it's able to do at least 90% of all ports? Is there any combination of ports that are bundled together asic-wise or channelwise on the 6704, or are all ports equal in respect to each other?

From what I've read, the 6704 has two ports on each ASIC, and each ASIC is capable of 10Gb/s each when *not* helped by a dCEF720 daughter card. (So, you can do a total of 10Gb/s across ports 1 and 2 combined and 10Gb/s across 3 and 4 combined) I'm guessing the bottleneck is shoving enough data to the Supervisor and back to switch a packet centrally, which is why the daughtercard improves performance.

I might of couse be totally wrong, I'd like to see detailed block diagrams on cisco.com for this sort of thing so we know how fast the cards really are and also to aid in troubleshooting but I can't see it happening.

-- Ryan O'Connell - CCIE #8174 <ry@complicity.co.uk> - http://www.complicity.co.uk

I'm not losing my mind, no I'm not changing my lines, I'm just learning new things with the passage of time

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