:What Linus says is definitely true of non-x86 architectures, :such as Alpha, but I had thought (not to be confused with :"know for a fact") that the x86 was "sequentially :consistent", making Matt's optimization legal. : :I've definitely seen the statement in the Intel manuals :that writes are not reordered. Thus, if the :program on processor 1 writes X to location A followed :by Y to location B, then processor 2 is guaranteed to :see X in A (and not some old value) if it's seen Y in B.

Yes, that's what I thought too. Writes are not reordered, but remember that pentiums do speculative reads and out of order instruction execution as well. Apparently pentiums also do write buffering (rather then write to the cache synchronously).

http://developer.intel.com/drg/pentiumii/appnotes/831.htm

The above says:

* writes are ordered

* reads do not pass *conflicting* writes, which means they can pass non-conflicting writes. BROKEN!!!!!!!

* Instructions may execute out of order (if non conflicting)

* Writes can be buffered -- that is, the pending writes are pending going INTO the cache and not synchronously written to the cache as they are on, say, the later MIPS cpus.

What a grade-A screwup by Intel. Extremely annoying at the very least. Gimme a MIPS chip any day.