On 7/9/07, Hans Petter Selasky <hsel...@c2i.net> wrote:
Perhaps what happens is that the "*pDst.bRam = _UCPU;"
command clears the FIFO
contents of the USB interrupt endpoint in addition to clearing the stall!?
If the sequence is like this:
Write to interrupt endpoint.
Reply command is written to FIFO.
Clear interrupt endpoint stall.
There is no data to read, because the FIFO has been emptied as a part of the
Xiaofan Chen: Could you check the datasheet for the chip that is used, what
the stall command actually does?
Sorry that I have three more questions:
1) What is the correct method to correctly respond to clear halt feature request
in the firmware so that it can still recover from the stall?
2) For the host, how does it know that the buffer data is still correct if the
buffer is not cleared?
2) What cause the stall to happen in the first place?